This invention relates to wiring design for VLSI chips, and particularly to a method for partitioning wiring resources for connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels of hierarchy.
S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, New York, U.S.A. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
As chip circuit densities increase, design implementation cycles decrease, and performance requirements increase, custom design techniques are employed to drive the performance to required levels. It has become increasingly important to be able to physically partition the chip more effectively with the goal of doing physical design implementation on the individual partitions in parallel as well as doing the physical design between the partitions with the partitions abstracted. One of the problems encountered when employing a concurrent, independently iterative and parallel execution of a hierarchical design technique is that the physical design resources need to be partitioned among the design elements in such a way as to allow the elements physical implementation to proceed concurrently while insuring that the overall design integrity is maintained (i.e. no conflicts in resources is encountered once the elements are assembled on the chip). The techniques we had tried before were not effective until we came upon the improvements described herein for the design of IBM""s S/390 chipsets.
This disclosure describes a methodology for partitioning the wiring resource among individual physical elements of a hierarchical design in such a way as to allow the different elements (which can be at various levels of the hierarchy) to be physically wired concurrently while insuring that the overall complete design is free of shorts or other conflicts. The xe2x80x9cwiring contractxe2x80x9d is employed as a vehicle to pass wiring resource constraints across partitioned physical design elements as well as across the various levels of design hierarchy.
In accordance with the invention, our method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked wiring areas, including clock and power grid areas, leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated per wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires may increase for the power grid area to prevent a signal wire from having an xe2x80x9cactivexe2x80x9d wire on either side of the signal wire. In the interactive process, a vertical slice of the wiring resources used for the space above a macro entity is defined and the macro entity is checked with this context of the VLSI chip physical design above it. The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools. This blockage modeling tool handles the newer, more complex types of design ground rules, such as wire spacings that are functions of the wiresxe2x80x2 widths or wire spacing to via junction that are dependent on both the metal extension beyond the via junction and the width of the covering metal. It adds artificial blockages to guide the routing tools to wire a design without shorts or DRC violations when these situations force the spacings to be more than the xe2x80x9cabsolutexe2x80x9d minimum.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
FIG. 1 illustrates partitioning of a VLSI chip.
FIG. 2 illustrates some of the xe2x80x9cfixedxe2x80x9d wiring constraints that need to be managed and passed to the various levels of hierarchy.
FIG. 3 illustrates contracts generated for unit and chip levels of hierarchy (which are inverses of each other) to define regions where each level of hierarchy can and can""t wire.
FIG. 4 illustrates the wiring bays on two levels of metal.
FIG. 5 illustrates a technique by which the electrical coupling between signal nets can be minimized by allocation of tracks adjacent to the power rails to the physical hierarchy level which will tend to have the longest wires.
FIG. 6 illustrates a shadow generated for a specific macro design entity.
FIG. 7 illustrates the modification of the blockage model for a shape in a macro to account for complex spacing ground rules.